1. Field of the Invention
The present invention relates to contact interfaces on the surface of semiconductor substrates and methods of forming the same. More particularly, the present invention relates to forming silicide interfaces for use with thin film devices and backend integrated circuit (xe2x80x9cICxe2x80x9d) testing devices.
2. State of the Art
In the processing of integrated circuits, electrical contact must be made to isolated active-device regions formed within a semiconductor substrate, such as a silicon wafer. Such active-device regions may include p-type and n-type source and drain regions used in the production of NMOS, PMOS, and CMOS structures for production of DRAM chips and the like. The active-device regions are connected by conductive paths or lines which are fabricated above an insulative or dielectric material covering a surface of the semiconductor substrate. To provide electrical connection between the conductive path and the active-device regions, openings in the insulative material are generally provided to enable a conductive material to contact the desired regions, thereby forming a xe2x80x9ccontact.xe2x80x9d The openings in the insulative material are typically referred to as xe2x80x9ccontact openings.xe2x80x9d
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are goals of the computer industry. However, as components become smaller and smaller, tolerances for all semiconductor structures (such as circuitry traces, contacts, dielectric thickness, and the like) become more and more stringent. In fact, each new generation of semiconductor device technology has seen a reduction in contact size of, on average, about 0.7 times. Further, the reduction in size of integrated circuits also results in a reduction in the height of the integrated circuits.
Of course, the reduction in contact size (i.e., diameter) has resulted in a greatly reduced area of contact between the active-device regions and the conductive material. Regardless of the conductive material used to fill these small contact openings to form the contacts (such as tungsten or aluminum), the interface between the conductive material and active-device region must have a low resistance.
Various methods have been employed to reduce the contact resistance at the interface between the conductive material and active-device region. One such method includes the formation of a metal silicide contact interface atop the active-device region within the contact opening prior to the application of the conductive material into the contact opening. A common metal silicide material formed is cobalt silicide (CoSix, wherein x is predominately equal to 2) generated from a deposited layer of cobalt. Cobalt silicide is preferred for shallow junctions of thin film structures because it forms very smooth, fine grained silicide, and will not form tightly bonded compounds with arsenic or boron atoms used in the doping of shallow junctions.
FIGS. 27-31 illustrate a common method of forming a cobalt silicide layer on an active-device region of a thin film semiconductor device. FIG. 27 illustrates an intermediate structure 400 comprising a semiconductor substrate 402 with a polysilicon layer 404 thereon, wherein the polysilicon layer 404 has at least one active-device region 406 formed therein with a thin dielectric layer 408, such as tetraethyl orthosilicatexe2x80x94TEOS, disposed thereover. The dielectric layer 408 must be as thin as possible to reduce the height of the thin film semiconductor device. A contact opening 412 is formed, by any known technique, such as patterning and etching, in the dielectric layer 408 to expose a portion of the active-device region 406, as shown in FIG. 28. A thin layer of cobalt 414 is applied over the dielectric layer 408 and the exposed portion of the active-device region 406, as shown in FIG. 29. A high temperature anneal step is conducted in an inert atmosphere to react the thin cobalt layer 414 with the active-device region 406 in contact therewith which forms a cobalt silicide layer 416, as shown in FIG. 30. However, dielectric materials, such as TEOSxe2x80x94tetraethyl orthosilicate, BPSGxe2x80x94borophosphosilicate glass, PSGxe2x80x94phosphosilicate glass, and BSGxe2x80x94borosilicate glass, and the like, are generally porous. Thus, the thin dielectric layer 408 has imperfections or voids which form passages through the thin dielectric layer 408. Therefore, when the high temperature anneal is conducted, cobalt silicide also forms in these passages. The cobalt silicide structures in the passages are referred to as patches 418, as also shown in FIG. 30. When the non-reacted cobalt layer 414 is removed to result in a final structure 422 with a cobalt silicide layer 416 formed therein, as shown in FIG. 31, the patches 418 also form conductive paths between the upper surface of the thin dielectric layer 408 which can cause shorting and current leakage on IC backend testing devices which leads to poor repeatability and, thus, poor reliability of the data from the testing devices.
Although such voids can be eliminated by forming a thicker dielectric layer 424, the thicker dielectric layer 424 leads to poor step coverage of the cobalt material 426 in bottom corners 428 of the contact opening 412, as shown in FIG. 32. The poor step coverage is cause by a build-up of cobalt material 426 on the upper edges 432 of the contact opening 412 which causes shadowing of bottom corners 428 of the contact openings 412. The result is little or no cobalt material 426 deposited at the bottom corners 428 of the contact opening 412 and consequently an inefficient silicide contact formed after annealing.
Step coverage can be improved by using filtering techniques, such as physical collimated deposition and low-pressure long throw techniques, which are used to increase the number of sputtered particles contacting the bottom of the contact opening. However, such filtering techniques are costly and the equipment is difficult to clean. Furthermore, filtering techniques also reduce the deposition rate of the cobalt material which reduces product throughput and, in turn, increases the cost of the semiconductor device. Moreover, using a thick dielectric layer is counter to the goal of reducing semiconductor device size. Finally, a thick dielectric layer eliminates the ability of the structure to be used as a backend IC probing device since the contacts are too small and too deep in the dielectric material. This is a result of dielectric material not being scalable. As device geometries get smaller, the thickness of the dielectric cannot be reduced without the potential of shorting and/or formation of patches. Thus, contact size must be increased to allow probe tips to fit in contacts, which is counter to the goal of reducing semiconductor device size.
Thus, it can be appreciated that it would be advantageous to develop a technique and a contact interface which is free from patch formations, while using inexpensive, commercially-available, widely-practiced semiconductor device fabrication techniques and equipment without requiring complex processing steps
The present invention relates to methods of forming silicide interfaces for use with thin film devices and backend integrated circuit testing devices and structures so formed. The present invention is particularly useful when a porous dielectric layer is disposed between a silicon-containing substrate and a silicidable material deposited to form a silicide contact in a desired area. As previously discussed, dielectric layers may have imperfections or voids which form passages through the thin dielectric layer. Therefore, when the high temperature anneal is conducted to form the silicide contact from the reaction of the silicidable material and the silicon-containing substrate, a silicide material may also form in these passages through the dielectric material. Such silicide material extending through these passages can cause shorting and current leakage. The present invention prevents the formation of silicide material through passages in the dielectric material by the application of a barrier layer between the dielectric material and the silicidable material.
In an exemplary method of forming a contact according to the present invention, a semiconductor substrate is provided with a polysilicon layer disposed thereon, wherein at least one active-device region is formed in a polysilicon layer. A thin dielectric layer is deposited or grown (such as by a thermal oxidation process) over the polysilicon layer and a layer of barrier material, preferably titanium nitride, is deposited over the thin dielectric layer.
A mask material is patterned on the barrier material layer and a contact opening is then etched through the barrier material layer and the thin dielectric layer, preferably by an anisotropic etch, to expose a portion of the active-device region. Any remaining mask material is removed and a thin layer of silicidable material, such as cobalt, titanium, platinum, or palladium, is deposited over the barrier material layer and into the contact opening over the exposed portion of the active-device region. A high temperature anneal is conducted to react the thin silicidable material layer with the active-device region in contact therewith, which forms a silicide contact. The barrier material prevents the formation of silicide structures within voids and imperfections in the thin dielectric layer. The non-reacted silicidable material layer and remaining barrier material layer are then removed.
In an exemplary method of forming a testing contact used in backend testing of semiconductor devices, a silicon-containing substrate is provided having at least one contact projection disposed thereon. A first dielectric layer is deposited or grown over the substrate and the contact projection. A layer of polysilicon is then deposited over the first dielectric layer. A second dielectric layer is optionally deposited over the polysilicon layer and a layer of barrier material is deposited over the optional second dielectric layer, or over the polysilicon, if the optional second dielectric layer is not used.
A mask material is patterned on the barrier material layer. The barrier material layer and the optional second dielectric layer (if used) are then etched to expose the polysilicon layer over the contact projection, then any remaining mask material is removed. A thin layer of silicidable material is deposited over the barrier material layer and onto the exposed contact projection. A high temperature anneal is conducted to react the thin silicidable material layer with the exposed portion of the polysilicon layer over the contact projection which forms a silicide layer. The non-reacted silicidable material layer and the remaining barrier material layer are then removed to form the testing contact.